Converged memory device and operation method thereof

ABSTRACT

A converged memory device includes: a first memory group having first characteristics; a second memory group having second characteristics that are different from the first characteristics; and a controller configured to migrate predetermined data of the second memory group into a cache region in the first memory group, wherein the controller is further configured to migrate data of the second memory group into the cache region by using the cache region as a buffer when an energy throttling operation is performed on the second memory group.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of U.S. patent applicationSer. No. 16/164,411, filed Oct. 18, 2018, and claims priority to KoreanPatent Application No. 10-2017-0142584, filed on Oct. 30, 2017, which isincorporated herein by reference in its entirety.

BACKGROUND 1. Field

Exemplary embodiments of the present disclosure relate to a convergedmemory device and a method for operating the converged memory device.

2. Description of the Related Art

Data are becoming most important assets in the fourth industrialrevolution, and the demands for new technology in support oftransferring and analyzing large-scale data at a high data rate areincreasing. For example, as artificial intelligence, autonomous driving,robotic, health care, virtual reality (VR), augmented reality (AR), andsmart home technologies are spreading, demands for servers or datacenters are increasing.

A legacy data center includes resources for computing, networking, andstoring data, in the same equipment. However, a future large-scale datacenter may construct resources individually and then logicallyrestructure the resources. For example, in the large-scale data center,the resources may be modularized at the level of racks, and themodularized resources may be restructured and supplied according totheir usage. Therefore, a converged storage or memory device, which canbe used for the future large-scale data center, is demanded.

SUMMARY

Embodiments of the present disclosure are directed to a converged memorydevice and an operation method thereof, which may improve the enduranceand performance of a plurality of memories included in a memory blademounted on a server system or a data processing system.

In accordance with an embodiment of the present invention, a convergedmemory device includes: a first memory group having firstcharacteristics; a second memory group having second characteristicsthat are different from the first characteristics; and a controllerconfigured to migrate predetermined data of the second memory group intoa cache region in the first memory group, wherein the controller isfurther configured to migrate data of the second memory group into thecache region by using the cache region as a buffer when an energythrottling operation is performed on the second memory group.

The energy throttling operation may include an operation of throttlingat least one of a temperature and a power of each of the first andsecond memory groups.

The converged memory device may further include: a thermal sensor thatis included in each of the first memory group and the second memorygroup, and the controller produces a temperature monitoring result bymonitoring the temperature of each of the first memory group and thesecond memory group with the thermal sensor, and performs the energythrottling operation based on the temperature monitoring result.

When the monitoring result reveals that a temperature of the cacheregion in the first memory group is equal to or higher than a thresholdvalue, the controller disables a use of the cache region.

When the monitoring result reveals that a temperature of a first memoryin the first memory group is equal to or higher than a threshold value,the controller uses the cache region as a data buffer of the firstmemory and stores data stored in the first memory in the cache region.

When the monitoring result reveals that a temperature of a second memoryin the second memory group is equal to or higher than a threshold value,the controller stores write data of the second memory in the cacheregion.

The controller may monitor power of each of the first memory group andthe second memory group, and performs the energy throttling operationbased on a power monitoring result.

The controller may monitor power of each of the first memory group andthe second memory group by monitoring at least one of data transactionand a peak current of each of the first memory group and the secondmemory group.

When the monitoring result reveals that the power of the cache region inthe first memory group is equal to or higher than a threshold value, thecontroller disables a use of the cache region.

When the monitoring result reveals that the power of a first memory inthe first memory group is equal to or higher than a threshold value, thecontroller uses the cache region as a data buffer of the first memoryand stores data stored in the first memory in the cache region.

When the monitoring result reveals that the power of a second memory inthe second memory group is equal to or higher than a threshold value,the controller stores write data of the second memory in the cacheregion.

The cache region may include one physical memory that is selected fromamong memories in the first memory group.

The cache region may include a logical memory that is formed ofparticular corresponding regions of memories in the first memory group.

The first characteristics and the second characteristics may include oneor both of storage capacity and latency.

The first memory group and the second memory group may include DynamicRandom Access Memories (DRAMs) and Phase-Change Random Access Memories(PCRAMs), respectively.

The first memory group and the second memory group may includePhase-Change Random Access Memories (PCRAMs) and flash memories,respectively.

When the energy throttling operation is performed on a second memory inthe second memory group, the controller may further perform an operationof controlling data transaction into the second memory.

The predetermined data may include a hot data.

In accordance with another embodiment of the present invention, aconverged memory device includes: a first memory group having firstcharacteristics; a second memory group having second characteristicsthat are different from the first characteristics; a third memory grouphaving third characteristics that are different from the firstcharacteristics and the second characteristics; and a controllerconfigured to migrate first predetermined data of the second memorygroup into a first cache region in the first memory group, and tomigrate second predetermined data of the third memory group into asecond cache region in the second memory group, wherein the controlleris further configured to migrate first data of the second memory groupinto the first cache region by using the first cache region as a bufferwhen an energy throttling operation is performed on the second memorygroup, and to migrate second data of the third memory group into thesecond cache region by using the second cache region as a buffer whenthe energy throttling operation is performed on the third memory group.

The energy throttling operation may include an operation of throttlingat least one of temperature and power.

The converged memory device may further include: a thermal sensor thatis included in each of the first memory group, the second memory group,and the third memory group, wherein the controller produces atemperature monitoring result by monitoring a temperature of each of thefirst memory group, the second memory group, and the third memory groupwith the thermal sensor, and performs the energy throttling operationbased on the temperature monitoring result.

When the temperature monitoring result reveals that a temperature of thefirst cache region in the first memory group is equal to or higher thana threshold value, the controller may flush data stored in the firstcache region into the second cache region and disables a use of thefirst cache region.

When the temperature monitoring result reveals that a temperature of afirst memory in the first memory group is equal to or higher than athreshold value, the controller may use the first cache region as a databuffer of the first memory and stores data stored in the first memory inthe first cache region.

When the temperature monitoring result reveals that a temperature of thesecond cache region in the second memory group is equal to or higherthan a threshold value, the controller may disable a use of the secondcache region.

When the temperature monitoring result reveals that a temperature in asecond memory in the second memory group is equal to or higher than athreshold value, the controller may store write data of the secondmemory in the first cache region.

When the temperature monitoring result reveals that a temperature of athird memory in the third memory group is equal to or higher than athreshold value, the controller may store write data of the third memoryin the second cache region.

The controller monitors power of each of the first memory group, thesecond memory group, and the third memory group, and perform the energythrottling operation based on a power monitoring result.

The controller may monitors power of each of the first memory group, thesecond memory group, and the third memory group by monitoring at leastone of a data transaction and a peak current of each of the first memorygroup, the second memory group, and the third memory group.

When the power monitoring result reveals that the power of the firstcache region in the first memory group is equal to or higher than athreshold value, the controller may flush data stored in the first cacheregion into the second cache region and disables a use of the firstcache region.

When the power monitoring result reveals that the power of a firstmemory in the first memory group is equal to or higher than a thresholdvalue, the controller may use the first cache region as a data buffer ofthe first memory and stores data stored in the first memory in the firstcache region.

When the power monitoring result reveals that the power of the secondcache region in the second memory group is equal to or higher than athreshold value, the controller may disable a use of the second cacheregion.

When the power monitoring result reveals that the power of a secondmemory in the second memory group is equal to or higher than a thresholdvalue, the controller may store write data of the second memory in thefirst cache region.

When the power monitoring result reveals that the power of a thirdmemory in the third memory group is equal to or higher than a thresholdvalue, the controller may store write data of the third memory in thesecond cache region.

The first cache region may include one physical memory that is selectedfrom among memories in the first memory group, and the second cacheregion may include one physical memory that is selected from amongmemories in the second memory group.

The first cache region may include a logical memory that is formed ofparticular corresponding regions of memories in the first memory group,and the second cache region may include a logical memory that is formedof particular corresponding regions of memories in the second memorygroup.

Each of the first characteristics to third characteristics may includeat least one of storage capacity and latency.

The first memory group may include Dynamic Random Access Memories(DRAMs), and the second memory group includes Phase-Change Random AccessMemories (PCRAMs), and the third memory group includes flash memories

When the energy throttling operation is performed on a memory in thesecond memory group or a memory in the third memory group, thecontroller may further performs an operation of controlling a datatransaction in the memory on which the energy throttling operation isperformed.

Each of the first and second predetermined data may include hot data.

In accordance with yet another embodiment of the present invention, amethod for operating converged memory device including a first memorygroup having first characteristics and a second memory group havingsecond characteristics that are different from the first characteristicsincludes: migrating predetermined data of the second memory group into acache region in the first memory group; and throttling energy of amemory in the second memory group by using the cache region as a buffer,and migrating data of the memory in the second memory group into thecache region when an energy throttling operation is performed on thememory in the second an energy throttling operation group.

The throttling of the energy of the memory in the second memory groupmay include throttling one or both of a temperature of the memory in thesecond memory group and a power of the memory in the second memorygroup.

The throttling of the energy of the memory in the second memory groupmay include: producing a temperature monitoring result by monitoring atemperature of each of the first memory group and the second memorygroup using a thermal sensor that is included in each of the firstmemory group and the second memory group, and throttling the temperatureof each of the first memory group and the second memory group based onthe temperature monitoring result.

The throttling of the energy of the memory in the second memory groupmay further includes: when the temperature monitoring result revealsthat a temperature of the cache region in the first memory group isequal to or higher than a threshold value, disabling a use of the cacheregion.

The throttling of the energy of the memory in the second memory groupmay further include: when the temperature monitoring result reveals thata temperature of a first memory in the first memory group is equal to orhigher than a threshold value, using the cache region as a data bufferof the first memory and storing data stored in the first memory in thecache region.

The throttling of the energy of the memory in the second memory groupmay include: when the monitoring result reveals that a temperature ofthe memory in the second memory group is equal to or higher than athreshold value, storing write data of the memory in the cache region.

The throttling of the energy of the memory in the second memory groupmay include: generating a power monitoring result by monitoring a powerof each of the first memory group and the second memory group andthrottling the energy of each of the first memory group and the secondmemory group based on the power monitoring result.

The throttling of the energy of the memory in the second group memoriesmay include: monitoring power of each of the first memory group and thesecond memory group by monitoring at least one of data transaction and apeak current of each of the first memory group and the second memorygroup.

The throttling of the energy of the memory in the second memory groupmay further include: when the power monitoring result reveals that thepower of the cache region in the first memory group is equal to orhigher than a threshold value, disabling a use of the cache region.

The throttling of the energy of the memory in the second memory groupmay further include: when the power monitoring result reveals that thepower of a first memory in the first memory group is equal to or higherthan a threshold value, using the cache region as a data buffer of thefirst memory and storing data stored in the first memory in the cacheregion.

The throttling of the energy of the memory in the second memory groupmay include: when the power monitoring result reveals that the power ofthe memory in the second memory group is equal to or higher than athreshold value, storing write data of the memory in the cache region.

The cache region may include one physical memory that is selected fromamong memories in the first memory group.

The cache region may include a logical memory that is formed ofparticular corresponding regions of memories in the first memory group.

Each of the first characteristics and the second characteristics mayinclude at least one of storage capacity and latency.

The first memory group and the second memory group may include DynamicRandom Access Memories (DRAMs) and Phase-Change Random Access Memories(PCRAMs), respectively.

The first memory group and the second memory group may includePhase-Change Random Access Memories (PCRAMs) and flash memories,respectively.

The throttling of the energy of the memory in the second memory groupmay further include: when the energy throttling operation is performedon the memory in the second memory group, performing an operation ofcontrolling data transaction into the memory.

The predetermined data may include a hot data.

In accordance with still another embodiment of the present invention, amethod for operating a converged memory device including a first memorygroup having first characteristics, a second memory group having secondcharacteristics that are different from the first characteristics, and athird memory group having third characteristics that are different fromthe first characteristics and the second characteristics includes:migrating first predetermined data of the second memory group into afirst cache region in the first memory group; migrating secondpredetermined data of the third memory group into a second cache regionin the second memory group; throttling an energy of a second memory inthe second memory group by using the first cache region as a buffer andmigrating data of the second memory into the first cache region when anenergy throttling operation is performed on the second memory; andthrottling an energy of a third memory in the third memory group byusing the second cache region as a buffer and migrating data of thethird memory into the second cache region when the energy throttlingoperation is performed on the third memory.

Each of the throttling of the energy of the second memory and thethrottling of the energy of the third memory may include: throttling atleast one of a temperature and a power.

The throttling of the energy of the second memory and the throttling ofthe energy of the third memory may include: producing a temperaturemonitoring result by monitoring a temperature of each of the firstmemory group, the second memory group, and the third memory group usinga thermal sensor that is included in each of the first memory group, thesecond memory group, and the third memory group, and throttling anenergy of each of the first memory group, the second memory group, andthe third memory group based on the temperature monitoring result.

The throttling of the energy of the second memory and the throttling ofthe energy of the third memory may further include: when the temperaturemonitoring result reveals that a temperature of the first cache regionin the first memory group is equal to or higher than a threshold value,flushing data stored in the first cache region into the second cacheregion and disabling a use of the first cache region.

The throttling of the energy of the second memory and the throttling ofthe energy of the third memory may further include: when the temperaturemonitoring result reveals that a temperature of a first memory in thefirst group memories is equal to or higher than a threshold value, usingthe first cache region as a data buffer and storing data stored in thefirst memory in the first cache region.

The throttling of the energy of the second memory and the throttling ofthe energy of the third memory may further include: when the temperaturemonitoring result reveals that a temperature of the second cache regionis equal to or higher than a threshold value, disabling a use of thesecond cache region.

The throttling of the energy of the second memory and the throttling ofthe energy of the third memory may include: when the temperaturemonitoring result reveals that a temperature of the second memory isequal to or higher than a threshold value, storing write data of thesecond memory in the first cache region.

The throttling of the energy of the second memory and the throttling ofthe energy of the third memory may include: when the temperaturemonitoring result reveals that a temperature of the third memory isequal to or higher than a threshold value, storing write data of thethird memory in the second cache region.

The throttling of the energy of the second memory and the throttling ofthe energy of the third memory may include: monitoring power of each ofthe first memory group, the second memory group, and the third memorygroup, and throttling energy of each of the first memory group, thesecond memory group, and the third memory group based on a powermonitoring result.

The throttling of the energy of the second memory and the throttling ofthe energy of the third memory may include: monitoring power of each ofthe first memory group, the second memory group, and the third memorygroup by monitoring at least one of data transaction and a peak currentof each of the first memory group, the second memory group, and thethird memory group.

The throttling of the energy of the second memory and the throttling ofthe energy of the third memory may further include: when the powermonitoring result reveals that the power of the first cache region inthe first memory group is equal to or higher than a threshold value,flushing data stored in the first cache region into the second cacheregion and disabling a use of the first cache region.

The throttling of the energy of the second memory and the throttling ofthe energy of the third memory may further include: when the powermonitoring result reveals that the power of a first memory in the firstmemory group is equal to or higher than a threshold value, using thefirst cache region as a data buffer of the first memory and storing datastored in the first memory in the first cache region.

The throttling of the energy of the second memory and the throttling ofthe energy of the third memory may further include: when the powermonitoring result reveals that the power of the second cache region inthe second memory group is equal to or higher than a threshold value,disabling a use of the second cache region.

The throttling of the energy of the second memory and the throttling ofthe energy of the third memory may include: when the power monitoringresult reveals that the power of the second memory in the second memorygroup is equal to or higher than a threshold value, storing write dataof the second memory in the first cache region.

The throttling of the energy of the second memory and the throttling ofthe energy of the third memory may include: when the power monitoringresult reveals that the power of the third memory in the third memorygroup is equal to or higher than a threshold value, storing write dataof the third memory in the second cache region.

The first cache region may include one physical memory that is selectedfrom among memories in the first memory group, and the second cacheregion may include one physical memory that is selected from amongmemories in the second memory group.

The first cache region may include a logical memory that is formed ofparticular corresponding regions of memoires in the first memory group,and the second cache region may include a logical memory that is formedof particular corresponding regions of memories in the second memorygroup.

Each of the first characteristics to third characteristics may includeone or both of storage capacity and latency.

The first memory group includes Dynamic Random Access Memories (DRAMs),and the second memory group includes Phase-Change Random Access Memories(PCRAMs), and the third memory group may include flash memories.

The throttling of the energy of the second memory and the throttling ofthe energy of the third memory may further include: when the energythrottling operation is performed on the second memory or the thirdmemory, performing an operation of throttling a data transactioncharacteristic of the memory on which the energy throttling operation isperformed.

Each of the first and second predetermined data includes hot data.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a data processing system.

FIGS. 2 and 3 illustrate a computing device in accordance with anembodiment of the present disclosure.

FIG. 4 is a block diagram illustrating a compute blade in accordancewith an embodiment of the present disclosure.

FIGS. 5A and 5B are block diagrams illustrating memory blades inaccordance with embodiments of the present disclosure.

FIG. 6 is a block diagram illustrating a memory blade including a datacontroller in accordance with an embodiment of the present disclosure.

FIGS. 7A to 7C illustrate examples of memories of a memory blade inaccordance with embodiments of the present disclosure.

FIG. 8 is a block diagram illustrating a memory blade including a datacontroller in accordance with an embodiment of the present disclosure.

FIG. 9 is a block diagram illustrating a controller including a datacontroller in accordance with an embodiment of the present disclosure.

FIG. 10A illustrates an example of a hot page table in accordance withan embodiment of the present disclosure.

FIG. 10B illustrates an example of storing cache data in accordance withan embodiment of the present disclosure.

FIG. 11 is a block diagram illustrating a memory blade including a datacontroller in accordance with an embodiment of the present disclosure.

FIG. 12 is a flowchart briefly illustrating an operation of a memoryblade in accordance with an embodiment of the present disclosure.

FIG. 13 is a flowchart illustrating an operation of a memory blade indetail in accordance with an embodiment of the present disclosure.

FIGS. 14A to 14E illustrate an example of a throttling operation of amemory blade for throttling a temperature in accordance with anembodiment of the present disclosure.

FIG. 15 illustrates an example of using a hot page table as a table fora write buffer during a temperature throttling operation of a memoryblade in accordance with an embodiment of the present disclosure.

FIG. 16 is a block diagram illustrating a memory blade including a datacontroller in accordance with an embodiment of the present disclosure.

FIG. 17 is a flowchart briefly illustrating an operation of a memoryblade in accordance with an embodiment of the present disclosure.

FIG. 18 is a flowchart illustrating an operation of a memory blade indetail in accordance with an embodiment of the present disclosure.

FIGS. 19A to 19F are block diagrams illustrating a memory blade inaccordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION

Exemplary embodiments of the present disclosure will be described belowin more detail with reference to the accompanying drawings. The presentdisclosure may, however, be embodied in different forms and should notbe construed as limited to the embodiments set forth herein. Rather,these embodiments are provided so that this disclosure will be thoroughand complete, and will fully convey the scope of the present inventionto those skilled in the art. Throughout the disclosure, like referencenumerals refer to like parts throughout the various figures andembodiments.

FIG. 1 is a block diagram illustrating a data processing system 10.Referring to FIG. 1, the data processing system 10 may include aplurality of computing racks 20, a management interface 30, and anetwork 40 for communication between the computing racks 20 and themanagement interface 30. The data processing system 10 having thisrack-scale architecture may be used by a data center for processinglarge-scale data.

Each of the computing racks 20 may individually implement one computingdevice. Alternatively, each of the computing racks 20 may be combinedwith other computing racks to implement one computing device. Thespecific structures and operations of the computing racks 20 will bedescribed later on.

The management interface 30 may provide an interactive interface for auser to control, administrate, or manage the data processing system 10.The management interface 30 may be realized using an arbitrary type of acomputing device that includes any of a computer, a multi-processorsystem, a server, a rack-mount server, a blade server, a lap-topcomputer, a notebook computer, a tablet computer, a wearable computingdevice, a network device, a web device, a distributed computing system,a processor-based system, a consumer electronic device, and so on.

According to some embodiments of the present disclosure, the managementinterface 30 may be realized by a distributed system having operationfunctions which may be performed by the computing racks 20 or havinguser interface functions which may be performed by the managementinterface 30. According to other embodiments of the present disclosure,the management interface 30 may be realized by a virtual cloud serverthat includes multi-computing devices distributed through the network40. The management interface 30 may include a processor, an input/outputsubsystem, a memory, a data storage device, and a communication circuit.

The network 40 may transfer/receive data between the computing racks 20and the management interface 30 and/or between the computing racks 20.The network 40 may be realized by an appropriate number of various wiredand/or wireless networks. For example, the network 40 may include apublicly accessible global network, such as a wired or wireless LocalArea Network (LAN), a Wide Area Network (WAN), a cellular network,and/or the Internet. In addition, the network 40 may include anappropriate number of auxiliary network devices, such as auxiliarycomputers, routers, and switches.

FIG. 2 illustrates a computing device having a rack structure inaccordance with an embodiment of the present disclosure.

Referring to FIG. 2, a computing rack 20 may include constituentelements in various forms, and structures, shapes, and names of theconstituent elements are not limited. For example, the computing rack 20may include a plurality of drawers 21 to 29. Each of the drawers 21 to29 may include a plurality of modules, each of which may include aplurality of blades.

In various embodiments of the present disclosure, the computing rack 20may be realized by a combination of appropriate numbers of computeblades, memory blades, and/or interconnect blades. Herein, it is definedthat the computing rack 20 is realized by a combination of a pluralityof blades, but the computing rack 20 may also be realized by diverselynamed elements such as drawers, modules, trays, boards, sashes, orunits. The computing rack 20 may have a structure where the constituentelements of the computing rack 20 are disaggregated and classifiedaccording to their functions for the sake of convenience in realization.Although not limited, the computing rack 20 may have a structure of aninterconnect blade, a compute blade, and a memory blade in aclassification order from the top. The computing rack 20 and a computingdevice including the computing rack 20 may be referred to as ‘arack-scale system’ or ‘a disaggregated system.’

In an embodiment of the present disclosure, a computing device may berealized by one computing rack 20. In other embodiments, the computingdevice may be realized by all constituent elements of two or morecomputing racks 20, realized by some of constituent elements of two ormore computing racks 20, or some of constituent elements of onecomputing rack 20.

In various embodiments of the present disclosure, a computing device maybe realized by a combination of appropriate numbers of compute blades,memory blades, and interconnect blades that are included in thecomputing rack 20. As illustrated in FIG. 2, a computing rack 20A mayinclude two compute blades, three memory blades, and one interconnectblade. A computing rack 20B may include three compute blades, two memoryblades, and one interconnect blade. A computing rack 20C may include onecompute blade, four memory blades, and one interconnect blade.

Although FIG. 2 illustrates a case where the computing rack 20 isrealized by appropriate numbers of compute blades, memory blades, andinterconnect blades, the computing rack 20 may include additionalconstituent elements that may be included in typical servers, such as apower system, a cooling system, an input/output device, and so on.

FIG. 3 illustrates a computing device 100 in accordance with anembodiment of the present disclosure.

Referring to FIG. 3, the computing device 100 may include a plurality ofcompute blades 200, a plurality of memory blades 400, and aninterconnect blade 300. The compute blades 200 may be called pooledcompute blades or pooled compute systems. Similarly, the memory bladesmay be called pooled memory blades or pooled memory systems. Herein, itis defined that the computing device 100 is realized by a combination ofa plurality of blades, but the computing device 100 may also be realizedby diversely named elements such as drawers, modules, trays, boards,sashes, or units.

Each of the compute blades 200 may include one or more of processingelements such as a processor, a processing/control circuit, a CentralProcessing Unit (CPU), and so on.

Each of the memory blades 400 may include one or more memories, such asvolatile memories, non-volatile memories, or a combination thereof. Forexample, each of the memory blades 400 may include Dynamic Random AccessMemories (DRAMs), flash memories, memory cards, hard disk drives (HDDs),solid state drives (SSDs), or a combination thereof.

Each of the memory blades 400 may be divided, allocated, or designatedby and used by one or more processing elements that are included in eachof the compute blades 200. Also, each of the memory blades 400 may storeone or more operating systems (OS) that may be initialized and/orexecuted by the compute blades 200.

The interconnect blade 300 may include a communication circuit, acommunication device, or a combination thereof, which may be divided,allocated, or designated by and used by one or more processing elementsincluded in each of the compute blades 200. For example, theinterconnect blade 300 may be realized by an arbitrary number of networkinterface ports, interface cards, or interface switches. Theinterconnect blade 300 may use protocols related to one or more wiredcommunication technologies for communication. For example, theinterconnect blade 300 may support communication between the computeblades 200 and the memory blades 400 based on one or more of protocolssuch as PCIe (Peripheral Component Interconnect Express), QPI (QuickPathInterconnect), Ethernet, and the like.

FIG. 4 is a block diagram illustrating a compute blade 200 in accordancewith an embodiment of the present disclosure.

Referring to FIG. 4, the compute blade 200 may include one or moreCentral Processing Units (CPUs) 210, one or more local memories 220, andan input/output (I/O) interface 230.

The CPUs 210 may divide, allocate, or designate one or more memoryblades to be used, among the memory blades 400 illustrated in FIG. 3.Also, the CPUs 210 may initialize the one or more memory blades, andperform a data read operation and/or a data write (i.e., program)operation on the one or more memory blades.

The local memories 220 may store data to perform an operation of theCPUs 210. In various embodiments of the present disclosure, the localmemories 220 may be in a one-to-one correspondence with the CPUs 210.

The input/output interface 230 may support interfacing between the CPUs210 and the memory blades 400 through the interconnect blade 300 of FIG.3. The input/output interface 230 may use protocols related to one ormore wired communication technologies, output and transfer data from theCPUs 210 to the interconnect blade 300, and receive data inputted fromthe interconnect blade 300 to the CPUs 210. For example, theinput/output interface 230 may support communication between the CPUs210 and the interconnect blade 300 using one or more of protocols suchas PCIe (Peripheral Component Interconnect Express), QPI (QuickPathInterconnect), Ethernet, and the like.

FIGS. 5A and 5B are block diagrams illustrating a memory blade 400 inaccordance with an embodiment of the present disclosure.

Referring to FIG. 5A, the memory blade 400 may include a controller 410and a plurality of memories 420. The memories 420 may store (or write)data therein or output (or read out) stored data under the control ofthe controller 410. The memories 420 may include a first memory group420A, a second memory group 420B, and a third memory group 420C. Each ofthe first, second, and third memory groups 420A, 420B, and 420C mayinclude a multiplicity of memories. The first memory group 420A, thesecond memory group 420B, and the third memory group 420C may have thesame characteristics or different characteristics. In variousembodiments of the present disclosure, the first memory group 420A, thesecond memory group 420B, and the third memory group 420C may includememories having different characteristics in terms of capacity orlatency.

Referring to FIG. 5B, the first memory group 420A may include DynamicRandom Access Memories (DRAMs). The second memory group 420B may includePhase-Change Random Access Memories (PCRAMs). The third memory group420C may include flash memories.

The capacity characteristics may be in relationship of the first memorygroup 420A<second memory group 420B<third memory group 420C. The latencycharacteristics may be in relationship of the first memory group420A<second memory group 420B<third memory group 420C. In other words,the capacity of the third memory group 420C may be the greatest and thecapacity of the first memory group 420A may be the smallest, while thelatency of the first memory group 420A is the shortest and the latencyof the third memory group 420C may be the longest.

FIG. 5B illustrates a case where the first memory group 420A includesDRAMs, the second memory group 420B includes PCRAMs, and the thirdmemory group 420C includes flash memories, but embodiments are notlimited thereto. In other embodiments, it is possible that various formsof memories having different characteristics are used for the firstmemory group 420A, the second memory group 420B, and the third memorygroup 420C.

In some embodiments, when the third memory group 420C includes flashmemories, the first memory group 420A may include Static Random AccessMemories (SRAMs), and the second memory group 420B may include MagneticRandom Access Memories (MRAMs) or Spin Torque Transfer Random AccessMemories (STT-RAMs).

Referring back to FIG. 5A, the controller 410 may include a datacontroller 510, memory controllers MC 520A to 520C, and an input/output(I/O) interface 530.

The data controller 510 may control data that are transferred/receivedbetween the memories 420 and the compute blades 200 shown in FIG. 3. Forexample, in response to a write request or command, the data controller510 may receive write data from the compute blades 200 and control awrite operation for programming the write data in a corresponding memoryamong the memories 420. In a read operation, in response to a readrequest or command, the data controller 510 may read out data stored ina particular memory among the memories 420 and control the readoperation for outputting the read data to a corresponding compute bladeamong the compute blades 200.

The memory controllers 520A to 520C may be positioned between the datacontroller 510 and the memories 420 and support interfacing between thedata controller 510 and the memories 420. The memory controllers 520A to520C may include a first memory controller iMC0 520A, a second memorycontroller iMC1 520B, and a third memory controller iMC2 520C thatrespectively correspond to the first memory group 420A, the secondmemory group 420B, and the third memory group 420C included in thememories 420. The first memory controller iMC0 520A may be disposedbetween the data controller 510 and the first memory group 420A andsupport a data transfer/reception between the data controller 510 andthe first memory group 420A. The second memory controller iMC1 520B maybe disposed between the data controller 510 and the second memory group420B and support a data transfer/reception between the data controller510 and the second memory group 420B. The third memory controller iMC2520C may be disposed between the data controller 510 and the thirdmemory group 420C and support a data transfer/reception between the datacontroller 510 and the third memory group 420C. In the embodimentillustrated in FIG. 5B, when the third memory group 420C includes flashmemories, the third memory controller iMC2 520C may be a flashcontroller.

The input/output interface 530 may support interfacing between the datacontroller 510 and the compute blades 200 through the interconnect blade300 of FIG. 3. The input/output interface 530 may use one or moreprotocols related to wired communication technologies, transfer readdata from the data controller 510 to the interconnect blade 300, andtransfer write data from the interconnect blade 300 to the datacontroller 510. For example, the input/output interface 530 may supportcommunication between the data controller 510 and the interconnect blade300 based on one or more of protocols such as Peripheral ComponentInterconnect Express (PCIe), QuickPath Interconnect (QPI), Ethernet, andthe like.

As described above, a data processing system or a server system may havea structure in which a plurality of blades, e.g., compute blades andmemory or storage blades, are discriminatively installed in a unit rack.Herein, one memory blade may include a plurality of memories havingdifferent characteristics to fulfill various user workloads. In otherwords, one memory blade may be a converged memory device in which aplurality of memories, such as DRAMs, SRAMs, PCRAMs, MRAMs, STT-RAMs,and/or flash memories (e.g., NAND-type flash memories), are converged.The converged memory device may be applied to various usage modelsbecause memories included in the converged memory device may havedifferent characteristics.

Unlike a DRAM, a PCRAM and a flash memory that may be included in amemory blade may have limited endurance, and may be vulnerable in termsof a temperature and a power due to high energy consumption in a writeoperation. In short, the converged memory device may consume high powerwhen transferring data in a high bandwidth, and a data error rate may beincreased when the converged memory device develops a high temperaturedue to the high power usage. As a result, the converged memory devicemay be damaged by the high temperature and/or the high power.

Embodiments of the present disclosure, which will be described below,may improve the endurance of a certain memory, which requires orconsumes relatively high energy, in a converged memory device includinga plurality of memories, and may improve the performance of the certainmemory by decreasing the number of times that the certain memory is usedor operates. To this end, in embodiments of the present disclosure, someof the plurality of memories or some regions in the plurality ofmemories may be used as a cache region for the certain memory. Inparticular, overhead of data migration may be minimized by storingpredetermined data, e.g., a page of hot data, for the certain memory inthe cache region. Also, according to embodiments of the presentdisclosure, the energy consumption of each of the plurality of memoriesmay be monitored and, if necessary, an energy throttling operation maybe performed.

For example, according to embodiments of the present disclosure, atemperature and/or a power of each of the plurality of memories may bemonitored and a throttling operation for throttling the temperatureand/or power of each of the plurality of memories may be performed.According to embodiments of the present disclosure, the vulnerability ofa memory to high temperature and power consumption may be improved byvariably using some of the plurality of memories or some regions in theplurality of memories, which are designated as the cache region, as awrite buffer or a temporary data buffer for the memory during thethrottling operation performed for the memory.

A throttling operation for a first memory (e.g., a PCRAM, a flashmemory, or the like) may reduce a temperature or average powerconsumption for the first memory by migrating data stored in the firstmemory, which consumes relatively high energy, into a preset cacheregion in a second memory (e.g., a DRAM, an SRAM, or the like), whichconsumes relatively low energy, and storing the migrated data in thecache region. Through the operation of migrating the data to the cacheregion, the number of times that a transaction is performed on the firstmemory, the number of times that the first memory is used, and thenumber of times that the first memory operates may be decreased.Furthermore, an operation frequency of the first memory may bedecreased. In addition, a cycle of a command to operate the first memorymay be longer. As a result of the throttling operation, the energyconsumption of the first memory may be reduced or minimized. Therefore,a throttling operation for a memory in accordance with embodiments ofthe present disclosure may be understood as an operation of minimizingor reducing the energy consumption for the memory, which consumesrelatively high energy.

FIG. 6 is a block diagram illustrating a memory blade 400 including acontroller 410 in accordance with an embodiment of the presentdisclosure.

Referring to FIG. 6, the memory blade 400 may include the controller 410and memories 420. The memories 420 may include a first memory group420A, a second memory group 420B, and a third memory group 420C thathave different characteristics in, e.g., storage capacity and latency.The first memory group 420A may include DRAMs having firstcharacteristics, the second memory group 420B may include PCRAMs havingsecond characteristics, the second characteristics being different fromthe first characteristics, and the third memory group 420C may includeflash memories having third characteristics, the third characteristicsbeing different from the first characteristics and the secondcharacteristics.

The controller 410 may include a data controller 510, memory controllersMC 520A to 520C, and an input/output (I/O) interface 530. Since thememory blade 400 in FIG. 6 includes the same constituent elements as theconstituent elements of the memory blade 400 illustrated above in FIG.5B, detailed description on the same constituent elements in the memoryblade 400 in FIG. 6 may be omitted herein, and a specific structure ofthe data controller 510 will be described below.

The data controller 510 may include a data agent 610 and a cache agent620. The data agent 610 may transfer/receive data for a write operationand/or a read operation between the controller 410 and the memories 420.The cache agent 620 may use a predetermined region in the memories 420as a cache region.

In various embodiments of the present disclosure, the cache agent 620may use a predetermined region in the first memory group 420A as a firstcache region for the second memory group 420B. Also, the cache agent 620may use a predetermined region in the second memory group 420B as asecond cache region for the third memory group 420C. Also, the cacheagent 620 may perform a cache control operation for managing leastrecently used data while using the cache region.

FIGS. 7A to 7C illustrate examples of memories of a memory blade inaccordance with an embodiment of the present disclosure.

Referring to FIG. 7A, the memory blade, e.g., the memory blade 400 inFIG. 6, may use memories 420 to form a main memory 710, a persistentmemory 720, and a storage 730. In other embodiments, the memory blade400 may use the memories 420 only as a main memory, or as a convergenceof a main memory and a storage.

Referring to FIG. 7B, the main memory 710 may include a first memorygroup, which includes k DRAMs, among the memories 420. The persistentmemory 720 may include a second memory group, which includes m PCRAMs,among the memories 420. The storage 730 may include a third memorygroup, which includes n flash memories, among the memories 420. Each ofK, m, and n is a positive integer.

In various embodiments of the present disclosure, a k^(th) DRAM amongthe k DRAMs in the main memory 710 may be selected and used as a firstcache region 740 for the PCRAMs in the persistent memory 720, and anm^(th) PCRAM among the m PCRAMs in the persistent memory 720 may beselected and used as a second cache region 750 for the flash memories inthe storage 730. In short, one physical memory among the memories ineach of the main memory 710 and the persistent memory 720 may be used asa cache region. The above-described method of using the cache region maycontribute improving the endurance and performance of PCRAMs and flashmemories (e.g., NAND flash memories).

Referring to FIG. 7C, particular corresponding regions of the k DRAMs inthe main memory 710 may be selected and used as a first cache region 745for the PCRAMs in the persistent memory 720, and particularcorresponding regions of the m PCRAMs in the persistent memory 720 maybe selected and used as a second cache region 755 for the flash memoriesin the storage 730. In short, a logical memory formed of the particularcorresponding regions of the memories in each of the main memory 710 andthe persistent memory 720 may be used as a cache region.

FIG. 8 is a block diagram illustrating a memory blade 400 including adata controller 510 in accordance with an embodiment of the presentdisclosure.

Referring to FIG. 8, the memory blade 400 may include the controller 410and memories 420. The memories 420 may include a first memory group420A, a second memory group 420B, and a third memory group 420C thathave different characteristics in, e.g., storage capacity and latency.The first memory group 420A may include DRAMs having firstcharacteristics, the second memory group 420B may include PCRAMs havingsecond characteristics, the second characteristics being different fromthe first characteristics, and the third memory group 420C may includeflash memories having third characteristics, the third characteristicsbeing different from the first characteristics and the secondcharacteristics. The controller 410 may include the data controller 510,memory controllers MC 520A to 520C, and an input/output (I/O) interface530. Since the memory blade 400 in FIG. 8 includes the same constituentelements as the constituent elements of the memory blade 400 illustratedin FIG. 5B, detailed description on the same constituent elements in thememory blade 400 in FIG. 8 may be omitted herein, and a specificstructure of the data controller 510 will be described below.

The data controller 510 may include a cache agent 620 and asupercapacitor 630. The cache agent 620 may use a predetermined regionin the memories 420 as a cache region. Also, the cache agent 620 mayperform a cache control operation for managing data, e.g., leastrecently used data, while using the cache region.

In various embodiments of the present disclosure, as illustrated inFIGS. 6, 7B, and 7C, the cache agent 620 may use a predetermined regionin the first memory group 420A as a first cache region for the secondmemory group 420B. Also, the cache agent 620 may use a predeterminedregion in the second memory group 420B as a second cache region for thethird memory group 420C.

The supercapacitor 630 may be employed to prevent data loss and recoverdata by performing a flush operation onto data stored in a cache region,e.g., in the DRAMs 420A, even when a power supply is cut off, such as asudden power off (SPO). In various embodiments of the presentdisclosure, the supercapacitor 630 makes it possible to flush the datastored in the cache region of the DRAMs 420A even when the power supplyis cut off. The supercapacitor 630 is used as a back-up power supplyunit for sufficiently supplying a power source to memories of aparticular group that include the cache region although the power supplyis cut off.

Although it is not shown in FIG. 8, the data controller 510 includes adata agent, which corresponds to the data agent 610 in FIG. 6. The dataagent may transfer/receive data for a write operation and/or a readoperation between the controller 410 and the memories 420.

FIG. 9 is a block diagram illustrating a controller 410 including a datacontroller 510 in accordance with an embodiment of the presentdisclosure.

Referring to FIG. 9, the controller 410 may include the data controller510, memory controllers MC 520A to 520C, and an input/output (I/O)interface 530.

The data controller 510 may include a cache agent 620 and a hot pagetable 640. The cache agent 620 may use, as a cache region, apredetermined region in memories (not shown), which may correspond tothe memories 420 described above with reference to FIGS. 6 and 8. Also,the cache agent 620 may perform a cache control operation for managing,e.g., least recently used data, while using the cache region.

In various embodiments of the present disclosure, as illustrated inFIGS. 6, 7B, and 7C, the cache agent 620 may use a predetermined regionin the first memory group 420A as a first cache region for the secondmemory group 420B. Also, the cache agent 620 may use a predeterminedregion in the second memory group 420B as a second cache region for thethird memory group 420C.

Although it is not shown in FIG. 9, the data controller 510 includes adata agent, which corresponds to the data agent 610 in FIG. 6, and thedata agent may transfer/receive data for a write operation and/or a readoperation between the controller 410 and the memories 420.

Since a write operation tends to be performed by converging ontoparticular addresses of the memories 420, the cache agent 620 may managepredetermined data, e.g., hot data, and migrate and store the hot datainto the cache region. In other words, the cache agent 620 may be ableto manage data by a page unit (e.g., approximately 4K-bit data) usingthe hot page table 640. Herein, although a case where the data migratedinto the cache region are hot data is described as an example, the cacheagent 620 may be able to migrate and store data in a different,predetermined appropriate form into the cache region.

FIG. 10A illustrates an example of a hot page table in accordance withan embodiment of the present disclosure. The storing and management ofthe hot page table may be carried out by a cache agent, e.g., the cacheagent 620 described above.

Referring to FIG. 10A, a hot page table 1010 may include HA, PA, FREQ,and VALID fields. HA may represent a host address requested for a writeoperation. For example, HA may be an address of the compute blade 200illustrated in FIG. 3 that is requested for the write operation. PA maybe a physical address of a memory that is requested for the writeoperation.

FREQ may represent a write request frequency count for an address. Forexample, a value of the FREQ field may be incremented when a writerequest for the address occurs. The value of the FREQ field may bedecreased at a predetermined time interval. When the value of the FREQfield is equal to or less than a predetermined count value, data of acorresponding page may be evicted from a cache region.

VALID may represent whether the data of the corresponding page arecached into the cache region or flushed from the cache region. Forexample, when a value of the VALID field is ‘1,’ it may represent thatthe data of the corresponding page are cached into the cache region. Onthe other hand, when the value of the VALID field is ‘0,’ it mayrepresent that the data of the corresponding page are flushed from thecache region.

For example, referring to FIG. 10A, in a case of a memory whose PA is‘0,’ write requests have occurred 100 times for the memory and dataaccording to the write requests have been cached into the cache regionof the memory, the value of the VALID field is ‘1.’ In a case of amemory whose PA is ‘2,’ write requests have occurred 200 times for thememory, and data according to the write requests have been cached intothe cache region of the memory, the value of the VALID field is ‘1.’ Onthe other hand, in a case of a memory whose PA is ‘1,’ write requestshave occurred 50 times for the memory, and data according to the writerequests have been evicted from the cache region of the memory, i.e.,the data according to the write requests have not been cached into thecache region, the value of the VALID field is ‘0.’

FIG. 10B illustrates an example of storing a group 1020 of cache data inaccordance with an embodiment of the present disclosure. The storing andmanagement of the cache data group 1020 may be carried out by a cacheagent, e.g., the cache agent 620 described above.

Referring to FIG. 10B, the cache data may be grouped into apredetermined size corresponding to an address and stored by a groupunit. For example, the cache data PA[0], PA[1], . . . , PA[11] may bestored on the basis of a page unit, which is a page including data,e.g., 4K-bit data. In other words, the cache data PA[0], PA[1], . . . ,PA[11] may be aligned on the basis of the page unit. The page 1020including the cache data PA[0], PA[1], . . . , PA[11] may be stored inthe cache regions 740 and 750, as illustrated in FIG. 7B, or stored inthe cache regions 745 and 755, as illustrated in FIG. 7C.

FIG. 11 is a block diagram illustrating a memory blade 400 including adata controller 510 in accordance with an embodiment of the presentdisclosure.

Referring to FIG. 11, the memory blade 400 may include a controller 410and memories 420. The memories 420 may include a first memory group420A, a second memory group 420B, and a third memory group 420C, whichhave different storage characteristics, e.g., different storage capacityand latency. The first memory group 420A may include DRAMs having firstcharacteristics, the second memory group 420B may include PCRAMs havingsecond characteristics, the second characteristics being different fromthe first characteristics, and the third memory group 420C may includeflash memories having third characteristics, the third characteristicsbeing different from the first characteristics and the secondcharacteristics. Each of the first memory group 420A, the second memorygroup 420B, and the third memory group 420C is provided with a thermalsensor (TS) 1100. The thermal sensor 1100 may be able to measure atemperature of a memory corresponding thereto.

The controller 410 may include the data controller 510, memorycontrollers MC 520A to 520C, and an input/output (I/O) interface 530.Since the memory blade 400 includes the same constituent elements as theconstituent elements of the memory blade 400 illustrated above in FIG.5B, detailed description on the same constituent elements describedabove may be omitted herein, and a specific structure of the datacontroller 510 will be described below.

The data controller 510 may include a cache agent 620, a hot page table640, and a thermal throttling agent 650. The cache agent 620 may use apredetermined region in the memories 420 as a cache region.

In various embodiments of the present disclosure, the cache agent 620may use a predetermined region in the first memory group 420A as a firstcache region for the second memory group 420B. Also, the cache agent 620may use a predetermined region in the second memory group 420B as asecond cache region for the third memory group 420C. Also, the cacheagent 620 may perform a cache control operation for managing, e.g.,least recently used data, while using the cache region.

The data controller 510 may include a data agent (not shown), whichcorresponds to the data agent 610 in FIG. 6. The data agent maytransfer/receive data for a write operation and/or a read operationbetween the controller 410 and the memories 420. The cache agent 620 mayuse a predetermined region among a portion of the storing regionsincluded in the memories 420 as a cache region. Also, the cache agent620 may perform a cache throttling operation (e.g., least recently useddata management) while using the cache region.

In various embodiments of the present invention, as illustrated in FIGS.6, 7B, and 7C, the cache agent 620 may use a predetermined region amongthe storing regions of the first memory group 420A as a cache region forthe second memory group 420B. Also, the cache agent 620 may use apredetermined region among the storing regions of the second memorygroup 420B as a cache region for the third memory group 420C.

Since a write operation tends to be performed by converging ontoparticular addresses of the memories 420, the cache agent 620 may managepredetermined data, e.g., hot data, and migrate and store the hot datainto the cache region. In other words, the cache agent 620 may be ableto manage data by a page unit using the hot page table 640. A page mayinclude 4K-bit data.

The thermal throttling agent 650 may monitor a temperature of each ofthe memories 420 by collecting temperature information of each of thememories 420 that is measured by the thermal sensors 1100 mounted on thefirst memory group 420A, the second memory group 420B, and the thirdmemory group 420C. Also, when the thermal throttling agent 650 decidesto control a temperature of a particular memory based on the collectedtemperature information, the thermal throttling agent 650 may perform atemperature throttling operation for the particular memory.

In various embodiments of the present disclosure, the thermal throttlingagent 650 may perform an operation of controlling the use of a cacheregion for a memory whose temperature is to be throttled. The thermalthrottling agent 650 interlocks with the cache agent 620 to perform theoperation of controlling the use of a cache region. For example, thethermal throttling agent 650 may perform an operation of changing theuse of a cache region for a memory whose temperature is to be throttled,such that the cache region is used as a write buffer or a temporary databuffer for the memory. Specific examples for the operation ofcontrolling the use of a cache region, which is performed by the thermalthrottling agent 650, will be described later with reference to FIGS.14A to 14E.

Also, the thermal throttling agent 650 may perform an operation ofthrottling a data transaction characteristic for the memory whosetemperature is to be throttled. For example, the thermal throttlingagent 650 may control the input/output interface 530 to decrease a datathroughput, a transmission rate, or a bandwidth of the memory whosetemperature is to be throttled.

Also, the thermal throttling agent 650 may adjust an operating speed ofa cooling fan (not shown), which is mounted on the memory whosetemperature is to be throttled. For example, the thermal throttlingagent 650 may be able to decrease a temperature of a high-temperaturememory by increasing an operating speed of a cooling fan mounted on thehigh-temperature memory.

When it is decided that a temperature of a particular memory should bethrottled, the above-mentioned operations performed by the thermalthrottling agent 650 of the data controller 510 may be sequentiallyperformed in an appropriate order. For example, the thermal throttlingagent 650 may perform a temperature throttling operation in the order ofadjusting a fan speed→controlling the usage of a cacheregion→controlling data transaction. Energy consumption of a memorywhose energy consumption is high due to a high temperature can bereduced by performing a temperature throttling operation on the memory.

FIG. 12 is a flowchart illustrating an operation 1200 of a memory bladein accordance with an embodiment of the present disclosure. Theoperation 1200 may be controlled by the data controller 510 illustratedin FIG. 11.

Referring to FIG. 12, the data controller 510 may perform a normaloperation in step 1210 and monitor a temperature of a memory in step1220. Herein, the normal operation may correspond to a case where thedata controller 510 manages hot-page data using a cache region while thedata controller 510 performs a write operation and a read operation ontothe first memory group 420A, the second memory group 420B, and the thirdmemory group 420C. The normal operation has been described above withreference to FIGS. 6 to 10B.

In various embodiments of the present disclosure, the thermal throttlingagent 650 of the data controller 510 may be able to monitor atemperature of each of the memories 420 by collecting temperatureinformation of each of the memories 420. For example, the temperaturesof the memories 420 are measured by the thermal sensors 1100 mounted onthe first memory group 420A, the second memory group 420B, and the thirdmemory group 420C. The temperatures are measured multiple times at apredetermined frequency, corresponding to a predetermined period.

The thermal throttling agent 650 may decide whether a temperature of aparticular memory should be throttled or not based on the collectedtemperature information in step 1230. When the thermal throttling agent650 decides that the temperature of the particular memory should bethrottled, the thermal throttling agent 650 may perform a temperaturethrottling operation onto the particular memory.

In various embodiments of the present disclosure, the thermal throttlingagent 650 may perform an operation of controlling the use of a cacheregion for the particular memory whose temperature is to be throttled,by being interlocked with the cache agent 620. For example, the thermalthrottling agent 650 may use a cache region as a write buffer or atemporary data buffer for the particular memory whose temperature is tobe throttled. The thermal throttling agent 650 is interlocked with thecache agent 620 to perform the operation of controlling the use of acache region.

In addition, the thermal throttling agent 650 may perform an operationof throttling a data transaction characteristic for the particularmemory whose temperature is to be throttled. For example, the thermalthrottling agent 650 may be able to control the input/output interface530 to decrease a data throughput, a transmission rate, or a bandwidthof the particular memory whose temperature is to be throttled.

Also, the thermal throttling agent 650 may adjust an operating speed ofa cooling fan (not shown) that is mounted on the particular memory whosetemperature is to be throttled. For example, the thermal throttlingagent 650 may be able to decrease a temperature of a high-temperaturememory by increasing an operating speed of a cooling fan mounted on thehigh-temperature memory.

When it is decided that the temperature of the particular memory shouldbe throttled, the above-mentioned operations performed by the thermalthrottling agent 650 of the data controller 510 may be sequentiallyperformed in an appropriate order. For example, the thermal throttlingagent 650 may perform a temperature throttling operation in the order ofadjusting a fan speed→controlling the usage of a cacheregion→controlling data transaction.

As described above, when the temperature of the particular memoryconsuming high energy should be throttled, the data controller 510 mayperform an operation of decreasing the temperature of the particularmemory by migrating and storing data for the particular memory, whichhas a relatively high energy consumption (e.g., a PCRAM, a flash memory,or the like), into a predetermined cache region of another memory, whichhas a relatively low energy consumption (e.g., a DRAM, an SRAM, or thelike). Through the operation of migrating and storing data, the numberof times that a transaction is performed on the particular memory, thenumber of times that the particular memory is used, the number of timesthat the particular memory operates, or a combination thereof, may bedecreased. In addition, the operation frequency of the particular memorymay be decreased. Furthermore, a cycle of an operation command foroperating the particular memory may be increased. As a result, theenergy consumption of the particular memory may be decreased orminimized.

FIG. 13 is a flowchart illustrating an operation 1300 of a memory bladein detail in accordance with an embodiment of the present disclosure.The operation 1300 may be controlled by the data controller 510illustrated in FIG. 11.

Referring to FIG. 13, the data controller 510 may perform a normaloperation in step 1310. Herein, the normal operation may correspond to acase where the data controller 510 performs an operation of managinghot-page data using a cache region while performing a write operationand a read operation on the first memory group 420A, the second memorygroup 420B, and the third memory group 420C, as described above withreference to FIGS. 6 to 10B.

The thermal throttling agent 650 of the data controller 510 may monitora temperature of each of the memories 420 and determine whether thetemperature of each of the memories 420 is equal to or higher than afirst threshold value THRESHOLD1 in step 1320. In various embodiments ofthe present disclosure, the thermal throttling agent 650 of the datacontroller 510 may be able to monitor the temperatures of the memories420 by collecting temperature information of each of the memories 420that is measured by the thermal sensors 1100 mounted on the first memorygroup 420A, the second memory group 420B, and the third memory group420C.

When it is decided that a temperature of a particular memory is equal toor higher than the first threshold value THRESHOLD1, the temperature ofthe particular memory should be throttled because it means that theenergy consumption of the particular memory is high. Therefore, when itis decided that the temperature of the particular memory is equal to orhigher than the first threshold value THRESHOLD1, the thermal throttlingagent 650 may detect identifier (ID) information of the particularmemory in step 1330, and perform a thermal throttling operation bycontrolling the use of a cache region for the particular memory in steps1340, 1350, and 1360.

A memory whose temperature is determined to be equal to or higher thanthe first threshold value THRESHOLD1 may be a cache DRAM that isdesignated as a cache region in the first memory group 420A, a normalDRAM that is not designated as a cache region in the first memory group420A, a cache PCRAM that is designated as a cache region in the secondmemory group 420B, a normal PCRAM that is not designated as a cacheregion in the second memory group 420B, or a memory in the third memorygroup 420C, i.e., a flash memory.

For the sake of convenience in description, embodiments of the presentdisclosure may be described by taking a case where a memory whosetemperature is determined to be equal to or higher than the firstthreshold value THRESHOLD1 is a cache DRAM which is designated as acache region in the first memory group 420A, a case where a memory whosetemperature is determined to be equal to or higher than the firstthreshold value THRESHOLD1 is a normal DRAM which is not designated as acache region in the first memory group 420A, and a case where a memorywhose temperature is determined to be equal to or higher than the firstthreshold value THRESHOLD1 is a normal PCRAM which is not designated asa cache region in the second memory group 420B. Specific examples on theoperation of the thermal throttling agent 650 controlling the use of acache region will be described by referring to FIGS. 14A to 14E.

When a particular memory whose temperature is determined to be equal toor higher than the first threshold value THRESHOLD1 is the cache DRAM inthe first memory group 420A (case (1) of the step 1340 in FIG. 13), thethermal throttling agent 650 may flush data stored in the cache DRAM bybeing interlocked with the cache agent 620 and disable the use of thecache DRAM as a cache region. In various embodiments of the presentdisclosure, the data stored in the cache DRAM may be flushed into acache region, e.g., 750 of FIG. 7B or 755 of FIG. 7B in the secondmemory group 420B.

When the particular memory is the normal DRAM in the first memory group420A (a case (2) of the step 1340 in FIG. 13), the thermal throttlingagent 650 may use the cache DRAM as a data buffer for the normal DRAM bybeing interlocked with the cache agent 620 (case (2) of the step 1350 inFIG. 13).

When the particular memory is the normal PCRAM in the second memorygroup 420B, the thermal throttling agent 650 may use the cache DRAM inthe first memory group 420A as a write buffer for the normal PCRAM bybeing interlocked with the cache agent 620 in step 1360.

Subsequently, the thermal throttling agent 650 may determine whether thetemperature of the particular memory whose cache usage has beencontrolled is equal to or higher than a second threshold valueTHRESHOLD2 in step 1370. When the temperature of the particular memoryis equal to or higher than the second threshold value THRESHOLD2, thethermal throttling agent 650 may perform an operation of throttling adata transaction characteristic for the particular memory in step 1380.For example, the thermal throttling agent 650 may control theinput/output interface 530 to decrease a data throughput, a transmissionrate, or a bandwidth of the particular memory whose temperature is to bethrottled.

In addition, although not illustrated and described herein, the thermalthrottling agent 650 may adjust an operating speed of a cooling fan (notshown) that is mounted on the particular memory whose temperature is tobe throttled. For example, the thermal throttling agent 650 may be ableto decrease a temperature of a high-temperature memory by increasing anoperating speed of a cooling fan mounted on the high-temperature memorythat is cooling the high-temperature memory.

In various embodiments of the present disclosure, the thermal throttlingagent 650 may set reference values so that the first threshold valueTHRESHOLD1 is smaller than the second threshold value THRESHOLD2. Thisrelationship is set in consideration of a case where a thermalthrottling operation fails even though the thermal throttling agent 650controls the use of a cache region. For example, even when the cacheregion 745 for a PCRAM illustrated in FIG. 7C is disabled in theoperation of controlling the use of a cache region, the temperature ofthe DRAMs in the main memory 710 may be increased as the access to theDRAMs is increased. In this case, the thermal throttling agent 650 mayperform a thermal throttling operation by controlling data transactionfor the DRAMs in the main memory 710 in step 1380.

FIGS. 14A to 14E illustrate an example of a throttling operation of amemory blade for throttling a temperature in accordance with anembodiment of the present disclosure. The operation 1300 described withreference to FIG. 13 may be performed by the cache agent 620 and thethermal throttling agent 650 of the data controller 510 illustrated inFIG. 11.

The thermal throttling agent 650 of the data controller 510 may monitorthe temperatures of the memories 420 and determine whether a temperatureof a particular memory is equal to or higher than a threshold valueTHRESHOLD or not. When it is determined that the temperature of theparticular memory is equal to or higher than the threshold valueTHRESHOLD, it may be a case where the energy consumption of theparticular memory is so high that a thermal throttling operation isneeded. The particular memory whose temperature is determined to beequal to or higher than the threshold value THRESHOLD may be a cacheDRAM designated as a cache region in the first memory group 420A, anormal DRAM that is not designated as a cache region in the first memorygroup 420A, a PCRAM designated as a cache region in the second memorygroup 420B, a normal PCRAM that is not designated as a cache region inthe second memory group 420B, or a memory in the third memory group420C, i.e., a flash memory.

Referring to FIG. 14A, when a temperature of a cache DRAM, e.g., DRAM k,which is designated as a first cache region in the first memory group420A, is equal to or higher than a threshold value THRESHOLD (e.g.,DRAMk High), the data controller 510 may flush data stored in the DRAM kinto a PCRAM designated as a second cache region in the second memorygroup 420B and disable the use of the DRAM k as the first cache region,in step 1410.

Referring to FIG. 14B, when a temperature of a normal DRAM, e.g., DRAM3, which is not designated as a cache region in the first memory group420A, is equal to or higher than a threshold value THRESHOLD (e.g.,DRAM3 High), the data controller 510 may use the first cache region,e.g., DRAM k, as a data buffer for the DRAM 3, and store data stored inthe DRAM 3 in the DRAM k, in step 1420.

Referring to FIG. 14C, when a temperature of a cache PCRAM, e.g., PCRAMm, designated as a second cache region in the second memory group 420Bis equal to or higher than a threshold value THRESHOLD (e.g., PCRAMmHigh), the data controller 510 may disable the use of the PCRAM m as thesecond cache region, in step 1430.

Referring to FIG. 14D, when a temperature of a normal PCRAM, e.g., PCRAM3, which is not designated as a cache region in the second memory group420B, is equal to or higher than a threshold value THRESHOLD (e.g.,PCRAM3 High), the data controller 510 may store write data for the PCRAM3 in the cache DRAM that is designated as the first cache region in thefirst memory group 420A, in step 1440. In short, the data controller 510may use the cache DRAM designated as the first cache region as a writebuffer for the PCRAM 3 of the high temperature in the second memorygroup 420B.

Referring to FIG. 14E, when a temperature of a flash memory, e.g., FLASH3, in the third memory group 420C is equal to or higher than a thresholdvalue THRESHOLD (e.g., FLASH3 High), the data controller 510 may storewrite data for the FLASH 3 into a cache PCRAM (PCRAM m) designated asthe second cache region in the second memory group 420B, in step 1450.In short, the data controller 510 may use the cache PCRAM designated asthe second cache region as a write buffer for the FLASH 3 of the hightemperature in the third memory group 420C.

FIG. 15 illustrates an example 1500 of using a hot page table as a tablefor a write buffer during a temperature throttling operation of a memoryblade in accordance with an embodiment of the present disclosure. Theexample 1500 may be controlled by the cache agent 620 and the thermalthrottling agent 650 of the data controller 510 illustrated in FIG. 11.

Referring to FIG. 15, the hot page table, which corresponds to the hotpage table 640 in FIG. 11, may be used as a table for a write bufferduring a thermal throttling operation, instead of being used as a bufferfor managing hot-page data in a cache region as illustrated in FIG. 10Ain a normal operation. For example, write data for a physical address(PA) 10 may be stored in the cache region, and write data for a physicaladdress 11 may be stored in the cache region, and write data for aphysical address 12 may be stored in the cache region, regardless of awrite request frequency count for each of the physical addresses 10, 11,and 12, i.e., regardless of whether the write data is hot data or not.In FIG. 15, a write request frequency count for each physical address is‘0.’

FIG. 16 is a block diagram illustrating a memory blade 400 including adata controller 510 in accordance with an embodiment of the presentdisclosure.

Referring to FIG. 16, the memory blade 400 may include a controller 410and memories 420. The memories 420 may include a first memory group420A, a second memory group 420B, and a third memory group 420C thathave different characteristics, e.g., different storage capacity andlatency. The first memory group 420A may include DRAMs having firstcharacteristics, the second memory group 420B may include PCRAMs havingsecond characteristics, the second characteristics being different fromthe first characteristics, and the third memory group 420C may includeflash memories having third characteristics, the third characteristicsbeing different from the first characteristics and the secondcharacteristics.

The controller 410 may include the data controller 510, memorycontrollers MC 520A to 520C, and an input/output (I/O) interface 530.Since the memory blade 400 includes the same constituent elements as theconstituent elements of the memory blades 400 illustrated above in FIG.5B, detailed description on the same constituent elements describedabove may be omitted herein, and a specific structure of the datacontroller 510 will be described below.

The data controller 510 may include a cache agent 620, a hot page table640, and a power throttling agent 660. The cache agent 620 may use apredetermined region in the memories 420 as a cache region. Also, thecache agent 620 may perform a cache control operation for managing,e.g., least recently used data, while using the cache region.

In various embodiments of the present disclosure, as illustrated inFIGS. 6, 7B, and 7C, the cache agent 620 may use a predetermined regionin the first memory group 420A as a first cache region for the secondmemory group 420B. Also, the cache agent 620 may use a predeterminedregion in the second memory group 420B as a second cache region for thethird memory group 420C.

Since a write operation tends to be performed by converging ontoparticular addresses of the memories 420, the cache agent 620 may managepredetermined data, e.g., hot data, and migrate and store the hot datainto the cache region. In other words, the cache agent 620 may be ableto manage data by a page unit (e.g., approximately 4K-bit data) usingthe hot page table 640.

The power throttling agent 660 may monitor the power for each of thememories 420 by collecting power information of each of memoriesincluded in the first memory group 420A, the second memory group 420B,and the third memory group 420C.

In various embodiments of the present disclosure, the power throttlingagent 660 may monitor the power for each of the memories 420 bycollecting data transaction information (e.g., an amount of write datathat is processed) of each of the memories included in the first memorygroup 420A and the second memory group 420B. Alternatively, the powerthrottling agent 660 may monitor the power for each of the memories 420by monitoring a peak current of each of the memories included in thefirst memory group 420A and the second memory group 420B. The peakcurrent of each of the memories 420 may be measured by a PowerManagement Integrated Circuit (PMIC).

Also, when it is decided based on the collected power information thatthe power of a particular memory should be throttled, the powerthrottling agent 660 may perform a power throttling operation for theparticular memory.

In various embodiments of the present disclosure, the power throttlingagent 660 may perform an operation of controlling the use of a cacheregion for the particular memory whose power is to be throttled, bybeing interlocked with the cache agent 620. For example, the powerthrottling agent 660 may perform an operation of changing a cache regionfor the particular memory whose power is decided to be throttled byinterlocking with the cache agent 620 into a write buffer. Specificexamples for the operation of controlling the use of a cache region,which is performed by the power throttling agent 660, are similar to theoperations that have been described above with reference to FIGS. 14A to14E.

Also, the power throttling agent 660 may perform an operation ofcontrolling data transaction for the particular memory whose power is tobe throttled. For example, the power throttling agent 660 may be able tocontrol the input/output interface 530 to decrease a data throughput, atransmission rate, or a bandwidth of the particular memory whose poweris to be throttled.

When it is decided that the power of the particular memory should bethrottled, the above-mentioned operations performed by the powerthrottling agent 660 of the data controller 510 may be sequentiallyperformed in an appropriate order or performed concurrently. Forexample, the power throttling agent 660 may perform a power throttlingoperation in the order of controlling the cache region usage→controllingdata transaction. It is possible to reduce the energy consumption of amemory whose energy consumption is increased due to excessive datatransaction, by performing the power throttling operation on the memory.

Although it is not shown in FIG. 16, the data controller 510 may includea data agent, which corresponds to the data agent 610 in FIG. 6, and thedata agent may transfer/receive data for a write operation and/or a readoperation between the controller 410 and the memories 420.

FIG. 17 is a flowchart briefly illustrating an operation 1700 of amemory blade in accordance with an embodiment of the present disclosure.The operation 1700 may be controlled by the data controller 510illustrated in FIG. 16.

Referring to FIG. 17, the data controller 510 may perform a normaloperation in step 1710 and monitor the power of a memory in step 1720.Herein, the normal operation may correspond to a case where the datacontroller 510 manages hot-page data in a cache region while the datacontroller 510 performs a write operation and a read operation onto thefirst memory group 420A, the second memory group 420B, and the thirdmemory group 420C. The normal operation has been described above withreference to FIGS. 6 to 10B.

In various embodiments of the present disclosure, the power throttlingagent 660 of the data controller 510 may be able to monitor the power ofeach of the memories 420 by collecting power information of each ofmemories included in the first memory group 420A, the second memorygroup 420B, and the third memory group 420C at a predetermined frequencycorresponding to a predetermined period.

In various embodiments of the present disclosure, the power throttlingagent 660 may monitor the power for the memories 420 by collecting datatransaction information (e.g., an amount of write data that isprocessed) of each of the memories included in the first memory group420A and the second memory group 420B. Also, the power throttling agent660 may monitor the power for the memories 420 by monitoring a peakcurrent of each of the memories included in the first memory group 420Aand the second memory group 420B. For example, the peak current of eachof the memories 420 may be measured by a Power Management IntegratedCircuit (PMIC). The power throttling agent 660 may measure the peakcurrent of each of the memories 420 or measure the peak currents of allthe memories 420 by using the PMIC or a substitutable means therefor.

The power throttling agent 660 may decide whether to perform a powerthrottling operation or not for a particular memory based on thecollected power information in step 1730. When it is decided that apower throttling operation should be performed on the particular memory,the power throttling agent 660 may perform the power throttlingoperation onto the particular memory.

In various embodiments of the present disclosure, the power throttlingagent 660 may perform an operation of controlling the use of a cacheregion for the particular memory whose power is to be throttled, bybeing interlocked with the cache agent 620 in step 1740. For example,the power throttling agent 660 may perform an operation of changing acache region for the particular memory whose power is decided to bethrottled by interlocking with the cache agent 620 into a write buffer.

In addition, the power throttling agent 660 may perform an operation ofcontrolling data transaction for the particular memory whose power is tobe throttled. For example, the power throttling agent 660 may be able tocontrol the input/output interface 530 to decrease a data throughput, atransmission rate, or a bandwidth of the particular memory whose poweris to be throttled.

When it is decided that the power of the particular memory should bethrottled, the above-mentioned operations performed by the powerthrottling agent 660 of the data controller 510 may be sequentiallyperformed in an appropriate order or performed concurrently. Forexample, the power throttling agent 660 may perform a power throttlingoperation in the order of controlling cache region usage→controllingdata transaction.

As described above, when it is decided that the power of the particularmemory consuming high energy should be throttled, the data controller510 may perform an operation of decreasing the average power of theparticular memory by migrating and storing data for the particularmemory that has a relatively high energy consumption (e.g., a PCRAM or aflash memory) into a predetermined cache region of a memory that has arelatively low energy consumption (e.g., a DRAM or an SRAM). Through theoperation of migrating and storing data, the number of times that atransaction is performed on the particular memory, the number of timesthat the particular memory is used, or the number of times that theparticular memory operates may be decreased, the operation frequency ofthe particular memory may be decreased, or a cycle of an operationcommand for operating the particular memory may be increased. As aresult, the energy consumption of the particular memory may be decreasedor minimized.

FIG. 18 is a flowchart illustrating an operation 1800 of a memory bladein detail in accordance with an embodiment of the present disclosure.The operation 1800 may be controlled by the data controller 510illustrated in FIG. 16.

Referring to FIG. 18, the data controller 510 may perform a normaloperation in step 1810. Herein, the normal operation may correspond to acase where the data controller 510 manages hot-page data in a cacheregion while the data controller 510 performs a write operation and aread operation onto the first memory group 420A, the second memory group420B, and the third memory group 420C. The normal operation has beendescribed above with reference to FIGS. 6 to 10B.

The power throttling agent 660 of the data controller 510 may monitorthe power of each of the memories 420 and determine whether the power ofeach of the memories 420 is equal to or higher than a first thresholdvalue THRESHOLD1 in step 1820.

In various embodiments of the present disclosure, the power throttlingagent 660 of the data controller 510 may be able to monitor the power ofeach of the memories 420 by collecting power information of each ofmemories included in the first memory group 420A, the second memorygroup 420B, and the third memory group 420C at a predeterminedfrequency, which corresponds to a predetermined period.

In various embodiments of the present disclosure, the power throttlingagent 660 may monitor the power for each of the memories 420 bycollecting data transaction information (e.g., an amount of write datathat is processed) of each of the memories included in the first memorygroup 420A and the second memory group 420B. Alternatively, the powerthrottling agent 660 may monitor the power for each of the memories 420by monitoring a peak current of each of the memories included in thefirst memory group 420A and the second memory group 420B. The peakcurrent of each of the memories 420 may be measured by a PowerManagement Integrated Circuit (PMIC).

The power throttling agent 660 may measure the peak current of each ofthe memories 420 or measure the peak currents of all the memories 420 byusing the PMIC or a substitutable means therefor.

When it is determined that the power for a particular memory is equal toor higher than the first threshold value THRESHOLD1, the energyconsumption of the particular memory is so high that a power throttlingoperation for onto the particular memory should be performed. When it isdetermined that the power for the particular memory is equal to orhigher than the first threshold value THRESHOLD1, the power throttlingagent 660 may detect identifier (ID) information of the particularmemory in step 1830, and perform the power throttling operation bycontrolling the use of a cache region for the particular memory in steps1840, 1850, and 1860.

The particular memory whose power is determined to be equal to or higherthan the first threshold value THRESHOLD1 may be a cache DRAM designatedas a cache region in the first memory group 420A, a normal DRAM that isnot designated as a cache region in the first memory group 420A, a cachePCRAM designated as a cache region in the second memory group 420B, anormal PCRAM that is not designated as a cache region in the secondmemory group 420B, or a memory in the third memory group 420C, i.e., aflash memory.

For the sake of convenience in description, a case where the particularmemory whose power is determined to be equal to or higher than the firstthreshold value THRESHOLD1 is a cache DRAM designated as a first cacheregion in the first memory group 420A, a case where the particularmemory is a normal DRAM that is not designated as the first cache regionin the first memory group 420A, and a case where the particular memoryis a normal PCRAM that is not designated as a second cache region in thesecond memory group 420B are described herein to describe embodiments ofthe present disclosure. Specific examples of the operation performed bythe thermal throttling agent 650 for controlling the use of a cacheregion are similar to the operations that have been described above byreferring to FIGS. 14A to 14E.

In the case where the particular memory whose power is determined to beequal to or higher than the first threshold value THRESHOLD1 is thecache DRAM designated as the first cache region in the first memorygroup 420A (case (1) of the step 1840 in FIG. 18), the power throttlingagent 660 may flush data stored in the cache DRAM by being interlockedwith the cache agent 620 and disable the use of the cache DRAM (case (1)of the step 1850 in FIG. 18) as the first cache region. In variousembodiments of the present disclosure, the data stored in the cache DRAMmay be flushed into a cache region, e.g., 750 of FIG. 7B or 755 of FIG.7C in the second memory group 420B.

In the case where the particular memory is the normal DRAM in the firstmemory group 420A (case (2) of the step 1840 in FIG. 18), the powerthrottling agent 660 may use the cache DRAM as a data buffer for thenormal DRAM by being interlocked with the cache agent 620 (case (2) ofthe step 1850 in FIG. 18).

In the case where the particular memory is the normal PCRAM in thesecond memory group 420B, the power throttling agent 660 may use thecache DRAM as a write buffer for the normal PCRAM by being interlockedwith the cache agent 620 in step 1860.

Subsequently, the power throttling agent 660 may determine whether thepower of the particular memory whose cache usage has been controlled isequal to or higher than a second threshold value THRESHOLD2 in step1870. When the power of the particular memory is equal to or higher thanthe second threshold value THRESHOLD2, the power throttling agent 660may perform an operation of controlling data transaction for theparticular memory in step 1880. For example, the power throttling agent660 may be able to control the input/output interface 530 to decrease adata throughput, a transmission rate, or a bandwidth of the particularmemory.

In various embodiments of the present disclosure, the power throttlingagent 660 may set reference values so that the first threshold valueTHRESHOLD1 is smaller than the second threshold value THRESHOLD2. Thisrelationship is set in consideration of a case where a power throttlingoperation fails even though the power throttling agent 660 controls theuse of a cache region. For example, even when the cache region 745 for aPCRAM illustrated in FIG. 7C is disabled in the operation of controllingthe use of the cache region, the power of the DRAMs in the main memory710 may be increased as the access to the DRAMs is increased. In thiscase, the power throttling agent 660 may perform a power throttlingoperation by controlling data transaction for the DRAMs in the mainmemory 710 in step 1880.

Meanwhile, the embodiments of the present disclosure described above maybe modified and used diversely. For example, the embodiments of thepresent disclosure described above illustrate the case where they areapplied to a converged memory device including a first memory grouphaving first characteristics, a second memory group having secondcharacteristics, which are different from the first characteristics, anda third memory group memories having third characteristics, which aredifferent from the first characteristics and the second characteristics.

Modified embodiments of the present disclosure may be applied to aconverged memory device as illustrated in FIGS. 19A to 19F. Referring toFIG. 19A, a converged memory device 400-1 may include a controller 410-1and memories 420-1. The memories 420-1 may include a first memory group420A having first characteristics, and a second memory group 420B havingsecond characteristics, which are different from the firstcharacteristics. The controller 410-1 may include a memory controller520A for the first memory group 420A and a memory controller 520B forthe second memory group 420B.

Referring to FIG. 19B, a converged memory device 400-1A may include acontroller 410-1A and memories 420-1A. The memories 420-1A may include afirst memory group 420A having first characteristics and a second memorygroup 420B having second characteristics, which are different from thefirst characteristics. The first memory group 420A may include DRAMs,and the second memory group 420B may include PCRAMs.

Referring to FIG. 19C, a converged memory device 400-1B may include acontroller 410-1B and memories 420-1B. The memories 420-1B may include afirst memory group 420A having first characteristics and a second memorygroup 420C having second characteristics, which are different from thefirst characteristics. The controller 410-1B may include a memorycontroller 520A for the first memory group 420A and a memory controller520C for the second memory group 420C. The first memory group 420A mayinclude DRAMs, and the second memory group 420C may include flashmemories.

Referring to FIG. 19D, a converged memory device 400-1C may include acontroller 410-1C and memories 420-1C. The memories 420-1C may include afirst memory group 420B having first characteristics and a second memorygroup 420C having second characteristics, which are different from thefirst characteristics. The controller 410-1C may include a memorycontroller 520B for the first memory group 420B and a memory controller520C for the second memory group 420C. The first memory group 420B mayinclude PCRAMs, and the second memory group 420C may include flashmemories.

Referring to FIG. 19E, a converged memory device 400-1D may include acontroller 410-1D and memories 420-1D. The memories 420-1D may include afirst memory group 420D having first characteristics and a second memorygroup 420B having second characteristics, which are different from thefirst characteristics. The controller 410-1D may include a memorycontroller 520D for the first memory group 420D and a memory controller520B for the second memory group 420B. The first memory group 420D mayinclude SRAMs, and the second memory group 420B may include PCRAMs.

Referring to FIG. 19F, a converged memory device 400-1E may include acontroller 410-1E and memories 420-1E. The memories 420-1E may include afirst memory group 420D having first characteristics and a second memorygroup 420C having second characteristics, which are different from thefirst characteristics. The controller 410-1E may include a memorycontroller 520D for the first memory group 420D and a memory controller520C for the second memory group 420C. The first memory group 420D mayinclude SRAMs, and the second memory group 420C may include flashmemories.

According to modified embodiments of the present disclosure, acontroller may store predetermined data, e.g., hot data, for a secondmemory group in a predetermined cache region in a first memory group,and when an energy throttling operation is to be performed on particularmemory in the second memory group, the controller may use the cacheregion in the first memory group as a buffer and store data for theparticular memory in the cache region.

According to modified embodiments of the present disclosure, the energythrottling operation may include an operation of throttling at least oneof temperature and power.

According to modified embodiments of the present disclosure, thecontroller may monitor a temperature of each of memories included in thefirst memory group and the second memory group using a thermal sensorincluded in each of the first memory group and the second memory group,and perform the energy throttling operation based on the temperaturemonitoring result.

According to modified embodiments of the present disclosure, when thetemperature monitoring result reveals that a temperature of the cacheregion in the first memory group is equal to or higher than a thresholdvalue, the controller may disable the use of the cache region.

According to modified embodiments of the present disclosure, when thetemperature monitoring result reveals that a temperature of a normalmemory in the first memory group is equal to or higher than thethreshold value, the controller may use the cache region in the firstmemory group as a data buffer for the normal memory and store datastored in the normal memory in the cache region.

According to modified embodiments of the present disclosure, when thetemperature monitoring result reveals that a temperature of a particularmemory in the second memory group is equal to or higher than thethreshold value, the controller may store write data for the particularmemory in the second memory group in the cache region in the firstmemory group.

According to modified embodiments of the present disclosure, thecontroller may monitor the power of each of the memories included in thefirst memory group and the second memory group and perform the energythrottling operation based on the power monitoring result.

According to modified embodiments of the present disclosure, thecontroller may monitor the power of each of the memories included in thefirst memory group and the second memory group by monitoring at leastone of data transaction and a peak current of each of the memoriesincluded in the first memory group and the second memory group.

According to modified embodiments of the present disclosure, when thepower monitoring result reveals that the power of the cache region inthe first memory group is equal to or higher than a threshold value, thecontroller may disable the use of the cache region.

According to modified embodiments of the present disclosure, when thepower monitoring result reveals that the power of a normal memory in thefirst memory group is equal to or higher than the threshold value, thecontroller may use the cache region in the first memory group as a databuffer for the normal memory and store data stored in the normal memoryin the cache region.

According to modified embodiments of the present disclosure, when thepower monitoring result reveals that the power of a particular memory inthe second memory group is equal to or higher than the threshold value,the controller may store write data for the particular memory in thecache region in the first memory group.

According to modified embodiments of the present disclosure, the cacheregion may include one physical memory that is selected from amongmemories in the first memory group.

According to modified embodiments of the present disclosure, the cacheregion may include a logical memory which is formed of particularcorresponding regions of memories in the first memory group.

According to modified embodiments of the present disclosure, firstcharacteristics and second characteristics of memories may include atleast one of storage capacity and latency.

According to modified embodiments of the present disclosure, the firstmemory group and the second memory group may include DRAMs and PCRAMs,respectively.

According to modified embodiments of the present disclosure, the firstmemory group and the second memory group may include PCRAMs and flashmemories, respectively.

According to modified embodiments of the present disclosure, when onememory requires an energy throttling operation, the controller mayfurther perform an operation of controlling a data transaction in thememory.

According to embodiments of the present disclosure, the endurance andperformance of a memory requiring or consuming a relatively high energyamong a plurality of memories included in a memory blade of a datacenter or a data processing system may be improved by decreasing thenumber of times that the memory requiring or consuming the relativelyhigh energy is used or operate. To this end, according to theembodiments of the present disclosure, some of memories or somecorresponding regions of the memories, except the memory requiring orconsuming the relatively high energy, may be used as a cache region forthe memory. Also, overhead of data migration may be minimized by storingpredetermined data (e.g., hot page) for the memory in the cache region.Also, according to embodiments of the present disclosure, the energyconsumption of each of memories in a memory blade may be monitored and,if necessary, an energy throttling operation may be performed on each ofthe memories. For example, according to embodiments of the presentdisclosure, a temperature and/or power of each of the memories may bemonitored and a throttling operation for throttling the temperatureand/or power of each of the memories may be performed. According to theembodiments of the present disclosure, weak points in terms oftemperature and power may be improved by variably using some of thememories or some corresponding regions of the memories, which aredesignated as a cache region, as a write buffer or a temporary databuffer during a throttling operation.

While the present invention has been described with respect to thespecific embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

What is claimed is:
 1. A converged memory device, comprising: a firstmemory group having first characteristics; a second memory group havingsecond characteristics that are different from the firstcharacteristics; a third memory group having third characteristics thatare different from the first characteristics and the secondcharacteristics; and a controller including a first interface forinterfacing with the first memory group, a second interface forinterfacing with the second memory group, and a third interface forinterfacing with the third memory group, wherein the controller isconfigured to migrate first predetermined data of the second memorygroup into a first cache region in the first memory group, and tomigrate second predetermined data of the third memory group into asecond cache region in the second memory group, and to monitor power ofeach of the first memory group, the second memory group and the thirdmemory group, wherein when the power monitoring result reveals that thepower of a second memory in the second memory group, which is physicallyseparated from the first memory group, is equal to or higher than athreshold value and an energy throttling operation is performed on thesecond memory group, the controller migrates first data of the secondmemory group into the first cache region through the second interfaceand the first interface by using the first cache region as a buffer, andwherein when the power monitoring result reveals that the power of athird memory in the third memory group, which is physically separatedfrom the second memory group, is equal to or higher than a thresholdvalue and the energy throttling operation is performed on the thirdmemory group, the controller migrates second data of the third memorygroup into the second cache region through the third interface and thesecond interface by using the second cache region as a buffer.
 2. Theconverged memory device of claim 1, further comprising: a thermal sensorthat is included in each of the first memory group, the second memorygroup, and the third memory group, wherein the controller produces atemperature monitoring result by monitoring a temperature of each of thefirst memory group, the second memory group, and the third memory groupwith the thermal sensor, and performs the energy throttling operationbased on the temperature monitoring result.
 3. The converged memorydevice of claim 2, wherein when the temperature monitoring resultreveals that a temperature of the first cache region in the first memorygroup is equal to or higher than a threshold value, the controllerflushes data stored in the first cache region into the second cacheregion and disables a use of the first cache region.
 4. The convergedmemory device of claim 2, wherein when the temperature monitoring resultreveals that a temperature of a first memory in the first memory groupis equal to or higher than a threshold value, the controller uses thefirst cache region as a data buffer of the first memory and stores datastored in the first memory in the first cache region.
 5. The convergedmemory device of claim 2, wherein when the temperature monitoring resultreveals that a temperature of the second cache region in the secondmemory group is equal to or higher than a threshold value, thecontroller disables a use of the second cache region.
 6. The convergedmemory device of claim 2, wherein when the temperature monitoring resultreveals that a temperature in a second memory in the second memory groupis equal to or higher than a threshold value, the controller storeswrite data of the second memory in the first cache region.
 7. Theconverged memory device of claim 2, wherein when the temperaturemonitoring result reveals that a temperature of a third memory in thethird memory group is equal to or higher than a threshold value, thecontroller stores write data of the third memory in the second cacheregion.
 8. The converged memory device of claim 1, wherein thecontroller monitors power of each of the first memory group, the secondmemory group, and the third memory group by monitoring at least one of adata transaction and a peak current of each of the first memory group,the second memory group, and the third memory group.
 9. The convergedmemory device of claim 1, wherein when the power monitoring resultreveals that the power of the first cache region in the first memorygroup is equal to or higher than a threshold value, the controllerflushes data stored in the first cache region into the second cacheregion and disables a use of the first cache region.
 10. The convergedmemory device of claim 1, wherein the first cache region includes onephysical memory that is selected from among memories in the first memorygroup, and the second cache region includes one physical memory that isselected from among memories in the second memory group.
 11. Theconverged memory device of claim 1, wherein the first cache regionincludes a logical memory that is formed of particular correspondingregions of memories in the first memory group, and the second cacheregion includes a logical memory that is formed of particularcorresponding regions of memories in the second memory group.
 12. Theconverged memory device of claim 1, wherein each of the firstcharacteristics to third characteristics include at least one of storagecapacity and latency.
 13. The converged memory device of claim 12,wherein the first memory group includes Dynamic Random Access Memories(DRAMs), and the second memory group includes Phase-Change Random AccessMemories (PCRAMs), and the third memory group includes flash memories.14. The converged memory device of claim 1, wherein when the energythrottling operation is performed on a memory in the second memory groupor a memory in the third memory group, the controller further performsan operation of controlling a data transaction in the memory on whichthe energy throttling operation is performed.
 15. The converged memorydevice of claim 1, wherein each of the first and second predetermineddata includes hot data.
 16. A method for operating a converged memorysystem including a first memory group having first characteristics, asecond memory group having second characteristics that are differentfrom the first characteristics, a third memory group having thirdcharacteristics that are different from the first characteristics andthe second characteristics, and a controller including a first interfacefor interfacing with the first memory group, a second interface forinterfacing with the second memory group, and a third interface forinterfacing with the third memory group, the method comprising:migrating first predetermined data of the second memory group into afirst cache region in the first memory group; migrating secondpredetermined data of the third memory group into a second cache regionin the second memory group; monitoring power of each of the first memorygroup, the second memory group and the third memory group; when thepower monitoring result reveals that the power of a second memory in thesecond memory group, which is physically separated from the first memorygroup, is equal to or higher than a threshold value and an energythrottling operation is performed on the second memory by using thefirst cache region as a buffer, migrating data of the second memory intothe first cache region through the second interface and the firstinterface; and when the power monitoring result reveals that the powerof a third memory in the third memory group, which is physicallyseparated from the second memory group, is equal to or higher than athreshold value and the energy throttling operation is performed on thethird memory by using the second cache region as a buffer, migratingdata of the third memory into the second cache region through the thirdinterface and the second interface.
 17. The method of claim 16, furthercomprising: producing a temperature monitoring result by monitoring atemperature of each of the first memory group, the second memory group,and the third memory group using a thermal sensor that is included ineach of the first memory group, the second memory group, and the thirdmemory group, and throttling an energy of each of the first memorygroup, the second memory group, and the third memory group based on thetemperature monitoring result.
 18. The method of claim 17, furthercomprising: when the temperature monitoring result reveals that atemperature of the first cache region in the first memory group is equalto or higher than a threshold value, flushing data stored in the firstcache region into the second cache region and disabling a use of thefirst cache region.
 19. The method of claim 17, further comprising: whenthe temperature monitoring result reveals that a temperature of a firstmemory in the first group memories is equal to or higher than athreshold value, using the first cache region as a data buffer andstoring data stored in the first memory in the first cache region. 20.The method of claim 17, further comprising: when the temperaturemonitoring result reveals that a temperature of the second cache regionis equal to or higher than a threshold value, disabling a use of thesecond cache region.
 21. The method of claim 17, wherein the methodincludes: when the temperature monitoring result reveals that atemperature of the second memory is equal to or higher than a thresholdvalue, storing write data of the second memory in the first cacheregion.
 22. The method of claim 17, wherein the method includes: whenthe temperature monitoring result reveals that a temperature of thethird memory is equal to or higher than a threshold value, storing writedata of the third memory in the second cache region.
 23. The method ofclaim 16, wherein the monitoring of the power of each of the firstmemory group, the second memory group and the third memory groupincludes: monitoring the power of each of the first memory group, thesecond memory group, and the third memory group, and throttling energyof each of the first memory group, the second memory group, and thethird memory group based on the power monitoring result.
 24. The methodof claim 16, wherein the monitoring of the power of the first memorygroup, the second memory group and the third memory group includes:monitoring the power of each of the first memory group, the secondmemory group, and the third memory group by monitoring at least one ofdata transaction and a peak current of each of the first memory group,the second memory group, and the third memory group.
 25. The method ofclaim 16, further comprising: when the power monitoring result revealsthat the power of the first cache region in the first memory group isequal to or higher than a threshold value, flushing data stored in thefirst cache region into the second cache region and disabling a use ofthe first cache region.
 26. The method of claim 16, wherein the firstcache region includes one physical memory that is selected from amongmemories in the first memory group, and the second cache region includesone physical memory that is selected from among memories in the secondmemory group.
 27. The method of claim 16, wherein the first cache regionincludes a logical memory that is formed of particular correspondingregions of memoires in the first memory group, and the second cacheregion includes a logical memory that is formed of particularcorresponding regions of memories in the second memory group.
 28. Themethod of claim 16, wherein each of the first characteristics to thirdcharacteristics include one or both of storage capacity and latency. 29.The method of claim 28, wherein the first memory group includes DynamicRandom Access Memories (DRAMs), and the second memory group includesPhase-Change Random Access Memories (PCRAMs), and the third memory groupincludes flash memories.
 30. The method of claim 16, further comprising:when the energy throttling operation is performed on the second memoryor the third memory, performing an operation of throttling a datatransaction characteristic of the memory on which the energy throttlingoperation is performed.
 31. The method of claim 16, wherein each of thefirst and second predetermined data includes hot data.